The Design of a 57-65GHz SPDT Switch with LC Resonant Techniques in 40 nm CMOS Process

This paper presents a single-pole double-throw (SPDT), transmit/receive (T/R) switch operating from 57 to 65GHz in 40 nm CMOS process. The SPDT is based on series-shunt transistors circuit with input and output matching networks. By using LC resonant techniques, the isolation of the switch in mil-limeter wave band can be improved by selecting appropriate res-onant inductors. The SPDT switch results in simulated insertion loss of 2.7dB at 60GHz and isolation is better than 28dB from 57 to 65GHz with return loss less than -13dB. With a control voltage of 1.2 V, the IP1dB of the switch is 12.7dBm at 60GHz. The core area size of switch is
$0.178\times 0.117$
mm2.