Design and Verification of 1X5 ROUTER

A router is a device that forwards the data packets along with the networks, commonly two LANs or WANs. It is an Open Systems Interconnection (OSI) layer 3 routing device. Depending on the address content in the incoming packets, this router routes a packet to an output channel. The packet has 3 parts, namely Header, payload and parity. In this project, a router of packet width 8 bits, payload length ranging from 1 byte to 31 bytes is implemented. This design is implemented in Verilog, verification is done using Universal Verification Methodology (UVM) and QuestaSim is used for functional coverage. This router consists of 4 submodules, namely First In First Out (FIFO), registers, Synchronizer and Finite State Machine (FSM). Five FIFOs are employed here and the final top module design is simulated and synthesized. The advantage of this router design is that it can receive only one packet at a time but five packets can be read out simultaneously.