Study of ESD Reliability on Gate and Drain to Source and substrate Stress by Structure Modulation in 0.18 μm 6 V nLDMOS Devices

The ESD strength of gate and drain to source and substrate stress in 0. $18 \mu m6V$ nLDMOS devices is studied in this paper. From the TLP measurement results we can observe that, firstly, as the length of the drift region increases, the trigger voltage $(V_{t1})$, the holding voltage $(V_{h)}$ and the second breakdown current $(I_{t2})$ will gradually increase. Secondly, as the length of the $\mathrm{S}\mathrm{H}_{-}\mathrm{P}$ region increases, the trigger voltage increases and has a saturation trend, the holding voltage has a little variation and the second breakdown current will gradually increase. Finally, from the test results for the HVPB modulation of the source region, from the test results the holding voltage increases little, the trigger voltage and secondary breakdown current have no obviously changes.