Hardware Implementation of an efficient FIR filter for ECG Signal Denoising Application

In this paper, an FIR filter using Vedic Multiplier and Carry Look Ahead adder (VMCLA) is proposed for Electrocardiogram (ECG) denoising. Vedic Multiplier based on Urdhva Tiryaghbhyam technique is designed because of its faster and better computational ability. Further, the delay in addition of partial products is also reduced by using Carry Look Ahead (CLA) Adder. ECG signal processing and validation of performance parameters are done in MATLAB. The proposed FIR filter design algorithm is synthesized and simulated using Vivado design suite 2021.2 and implemented on Kintex-7 FPGA board. The results revealed a high performance and area efficient compared to a well-known prior art filters.