8-bit Partial Magnitude Comparator for Spike Generation in the Leaky Integrate-and-Fire Neuron Model using Gate-Diffusion-Input Logic Gates

In an effort to reduce the power consumption required by artificial intelligence algorithms, many works take inspiration from biological neurons to develop spiking neural networks (SNN). The idea is to replace the currently used continuous neural output functions with low-energy spikes that are sparse in time. However, although possible in simulation, SNNs do not run efficiently on current hardware such as FPGAs, CPUs, or GPUs. This work presents a foundation for the development of a neuromorphic spiking neural network processor based on the Leaky Integrate-and-Fire (LIF) neuron model. A low-power digital spiking circuit is designed from an 8-bit partial magnitude comparator (PMC). The 8-bit PMC is made from modified Gate Diffusion Input (m-GDI) logic gates. When implemented in 65nm CMOS, it achieves an average power of
$4.51\mu W$
at a 1.2 V supply, and an average delay of 80.32ps. The spiking circuit has an average power of
$6.861\mu W$
and can operate at up to 14.28GHz. This spiking circuit is the first step towards the realization of a large-scale synchronous spiking neural network processor.