Spatial Degradation Profiling Technique in Self-Aligned Top-Gate a-InGaZnO TFTs Under Current-Flowing Stress

An analysis technique of quantitatively extrac- ting the spatial profile of the channel characteristics is proposed and utilized to observe the local electrical degradation in amorphous InGaZnO (a-IGZO) TFTs. Device degradation is observed by current–voltage and capacitance–voltage characteristics after applying stress with different gate (
${V}_{\textit {GS}}$
) and drain biases (
${V}_{\textit {DS}}$
) considering operation conditions. The asymmetry of device degradation becomes severe as
${V}_{\textit {DS}}$
for stress condition increases. In addition, after applying stress with the largest
${V}_{\textit {DS}}$
, a hump resulting from different types of degradation depending on location was observed: donor creation (
${2.5} \times {10}^{{18}}$
eV
$^{-{1}}$
cm
$^{-{3}}$
) near drain and electron trapping (
${2} \times {10}^{{12}}$
cm
$^{-{2}}$
) into gate insulator near source. The spatial profiling technique can be utilized as a quantitative analysis tool for stable TFT and circuit design for the various applications of displays.