Experimental validation of an analog spiking neural network with STDP learning rule in CMOS technology

We report the design in CMOS technology and the experimental characterization of an analog spiking neural network with on-chip unsupervised learning. Long-term synaptic memory is implemented using a floating-gate device in a standard 150 nm CMOS process. The neurons are operated with a voltage supply of only 0.4V, allowing an extremely low power dissipation with an energy dissipation per synaptic operation of about 55 fJ. The CMOS chip includes the circuits for implementing real-time learning of the network based on the Spike Time Dependent Plasticity algorithm. During the learning, the neurons produce pulses of ±4.5 V that change the synaptic weight by activating tunneling currents to change the charge in the floating gates.