Quantified tabbed lines and ground void impact on real DDR5 eye margin

Tabbed lines have been proposed to reduce or eliminate far-end crosstalk (FEXT) and impedance management [1], [2], [3] with the ground void beneath SMT connector landing pad implementation for DDR5 channel from simulation and tabbed transmission line measurement by a VNA or TDR. In this paper, a method to quantify the tabbed lines and ground void impact on real DDR5 eye margin is proposed. This method starts with the test board design with fours zones of tabbed, non-tabbed, void and non-void ground and follow up with impedance check by a TDR. The final step is to perform four zones memory margin result as comparison to quantify the tabbed lines and ground void impact on real DDR5 eye margin. [4], [5]. The quantified results could be good indicators for tabbed lines implementation decision and ground plane void patch mechanism.