A 13-bit Energy-Efficient SAR-Assisted Cyclic ADC for CMOS Image Sensor

This paper presents a 13-bit energy-efficient SAR-assisted cyclic ADC is proposed for CMOS image sensor. In this architecture, a 4-bit successive approximation register (SAR) ADC is used as a sub-ADC to achieve multi-bit quantization per cycle, thus it uses less capacitors than traditional SAR ADC and fewer cycles than traditional Cyclic ADC. In order to reduce power, a class AB output stage error amplifier is used to reduce quiescent bias current and asynchronous SAR logic is used to reduce system clock frequency. Three redundant bits are added to correct the non-linearity due to offset and settling error. The simulation result shows the peak DNL and INL of the proposed ADC is +0.2/-0.3LSB and +0.6/-0.5LSB. At a sample rate of 500kS/s, the ENOB is 12.17bit, the power is 72μW, and the FoM is 31.2fJ/conv.