Beyond Eliminating Timing Margin: An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator Without Accuracy Loss

Resilient circuits with timing error detection and correction (EDAC) can eliminate the excess timing margin but suffer from miss detection risk due to inactivation of the critical paths. We propose a negative margin timing error detection (NMED) method to increase detection reliability, which further pushes the timing margin to beyond eliminating it, by monitoring less critical yet often activated paths instead of the most critical but rarely activated paths. To further reduce its area overhead, we propose a low-overhead low-latency transition detector (TD) with only 16 transistors and a transmission gate-based short-path (SP) padding method to extend SPs efficiently. We implement all the proposed techniques on a neural network (NN) accelerator using the 28-nm CMOS process. Chip measurement results show that our NMED method achieves up to 238% frequency gain or 59% power reduction at near-threshold voltage (NTV) while solving the miss detection risk and conquering the accuracy loss problem in error detection of NN accelerators.