Predicting Transistor-level Hotspots with Thermal Resistance Metrics and Compact Thermal Models

In a semiconductor integrated circuit (IC), individual transistor junctions may be much hotter than traditional system-level thermal simulation techniques predict. In some cases, this underprediction can lead to reliability, functionality and performance concerns. While JEDEC-defined thermal resistance metrics and compact thermal models (CTM) can help chip manufacturers convey some information to system designers, a critical gap remains: these models are based on the concept of a single junction temperature, derived from an assumption of uniform power dissipation over the entire chip surface. While this may have been acceptable (if not entirely accurate) when these metrics and CTMs were developed and standardized, the gap between the predictions of thermal resistance metrics/CTMs and reality continues to widen, as ICs are produced on smaller geometry processes with ever increasing power densities. Coupled with higher ambient temperature requirements, the risk of ICs exceeding temperature limits is increasing. This paper discusses reasons why existing methods fail to accurately capture peak junction temperatures. Potential solutions that build upon the existing JEDEC thermal resistance metrics and CTMs are proposed.