Asynchronous Circuit Test IP Core Based on OLFSR and FPGA Implementation

As the integrated circuit design process enters the nanometer scale, the integration degree of the chip continues to improve. At the same time, the high level of integration leads to the increasingly complex design of the chip clock network. Asynchronous circuits are back on the designer's radar due to their clockless design approach. However, most of the current design tools and verification platforms are based on synchronous design. Therefore, it's important to achieve synchronous and asynchronous interactive design by using the existing synchronous design tools. By using the synchronous design tool Vivado and MicroZed development board, we propose the synthesizable asynchronous pseudo-random number generator to generate random number sequences conforming to the four-phase dual-rail protocol and the LEDR protocol, based on Optimized Linear Feedback Shift Register (OLFSR) pseudo-random number generation method. It provides convenience for the testing of synchronous and asynchronous circuits, and also provides a feasible design method process for the interactive design of synchronous and asynchronous circuits.