Characterization of Single Event Upsets of Nanoscale FDSOI Circuits Based on the Simulation and Irradiation Results

The advanced FDSOI technology has improved performance and inherent SEU resistance of integrated circuits, which is beneficial to the space applications. This paper provides the comprehensive characterization of SEU sensitivities based on the 3D-TCAD and SPICE simulations, as well as the irradiation results. We concentrate on the transient pulse, charge sharing, and collection effects of FDSOI circuits. The impact of strike location on transient features is evaluated in simulation, and the influence of charge sharing effects on SEU thresholds of SRAM is also analyzed. The SEU sensitive regions are characterized, which are closely related to the internal bipolar amplification effect and affected by the strike location. Additionally, the charge sharing effects are analyzed and verified by the combination of our circuit-level simulations and irradiation experiments based on the 256 Kbit pulse-mitigated SRAM. The split charge injection simulations show that the SEU threshold reduces about ~97% for the worst condition. Whereas, the actual SEU threshold of the pulse-mitigated FDSOI SRAM is not very small due to the limited charges shared by adjacent cells. The results provide a meaningful guidance for the radiation hardening design of FDSOI integrated circuits.