Synthesis of Synchronous Finite State Machines Operating on Both-Levels of the Clock Using Transparent Latches

In a synchronous digital system, the clock signal activity is a significant energy consumer. It consumes 15% to 45% of the energy consumed. Synchronous controllers are essential components in a digital system and use memory elements such as flip-flops to store the states and large consumers of energy. In this article, we propose a new approach for synthesizing synchronous controls for low consumption, which are implemented in architecture based on transparent latches and activated at both levels of the clock signal. Compared with transparent latches, the flip-flops increase the clock skew problem and affect performance because the setup and propagation times are more meaningful than the others. Through a case study, we present the proposed approach, with the synthesized synchronous controllers showing excellent potential to reduce the problems associated with the clock and operate at high speed due to latches.