Spur Reduction in Fractional PLL using Complementary PFD-CP technique for Wireless Transceiver Design

In this work, a design has been proposed to reduce the spurs in fractional PLLs operating at GHz range for wireless transceivers and other wireless communication applications. Two phase-frequency detectors and charge pumps are used driven by complementary clocks to generate opposite voltage profiles at separate instances across the common loop filter. By controlling the current in the delayed charge pump through a feedback loop, the voltage decays across the filter are canceled, and hence, spurs are reduced. Simulations are carried out in CMOS 180 nm technology for a 2.4 GHz PLL with fractional frequency division ratio of 0.1. Spurs are reduced to −29.5 dBc compared to −5 8 dBc in a conventional architecture.