Design of Low Power 4-Bit Baugh-Wooley Multiplier using 1-Bit Mirror and Approximate Full Adders

The majority of the most recent data-driven advancements, notably artificial-intelligence(AI) and machine-learning (ML) depend heavily on binary arithmetic computations. This paper focuses on the design and analysis of a reliable, low-power 4-bit Baugh-Wooley (BW) multiplier employing the high performance 1-bit mirror full-adder (MFA) and approximate full-adder (AFA). For a various technological nodes varying from 16 nm to 90 nm, the effectiveness of the proposed 4-bit BW multiplier is thoroughly investigated for power and delay parameters at different operating voltages (0.6 V – 1.0 V). The proposed 4-bit BW multiplier at a 16-nm CMOS process employing an MFA circuit consumes a minimal power of 37.5 μW at an operating voltage of 0.7 V and a nominal temperature of 30
⁰
C, whereas it consumes 35.5 μW for a combined MFA and AFA circuits. The power consumption increases linearly with operating voltage for the designed BW multiplier employing the two high performance full-adder circuits. The proposed 4-bit BW multiplier at 16-nm CMOS process has a delay of 104 ps at 0.7 V. The simulation result analysis indicates the combination of MFA and AFA circuits in the design of low-power 4-bit Baugh-Wooley multipliers, even though there exists a partial error at the output of multiplier MSB.