Virtual PCB Layout Prototyping: Importance of Modeling Gate Driver and Parasitic Capacitances

This paper presents a virtual prototype of a power electronics switching cell realized on a 4-layer printed circuit board (PCB) with a discrete SiC power MOSFET and a SiC Schottky diode. The main goal is to determine the modeling requirements for an accurate prediction of the actual switching losses and the potential coupling between the gate signal and the power loop due to PCB parasitic capacitances and inductances. The results point out that not only parasitic inductances are of interest but also parasitic capacitances, and that gate driver models have to be included for reliable virtual prototyping and layout design of power electronic PCBs.