The Functional Scheme of Hardware Semafore for Parallel Computing

The purpose of the article is to improve the performance of computing devices by hardware detection of the completion of operations. A hardware semaphore as a functional unit is built on the basis of the original shift register, which has several shift processes and a variable operating time. The coordinated simultaneous operation of the hardware semaphore and working functional nodes allows adaptively detecting the time points of the completion of the operation. Multiplexers have been introduced into the shift registers. They allow you to set several starting points and organize the process of detecting the completion of operations. A model test of the operating time of a hardware semaphore is carried out by a complete enumeration of operand options. The binary flag signals the readiness of the result. To do this, at the beginning of the operation, the flag is reset to logical “0”. At the end of the longest local process, the binary flag is set to logical “1”, which signals the completion of the entire operation. The parallel start of several local processes along the length of the processed operands leads to the absorption of the time of all processes, except for the longest one. The test showed the advantage of a hardware semaphore on average 1,8-2 times over a fixed time for completing operations. It is advisable to build a hardware semaphore into reconfigurable systems with data flow control.