Thermomechanical analysis of Si-chip fracture caused by double-sided Ag sintering for PCB embedded package

Previously, a novel concept for PCB embedding of power semiconductors with reinforced top contacts has been published by our group. In this work, a thermomechanical study is performed to understand the fracture probability of the chip during fabrication. The ball-on-ring (BOR) and ball-on-edge (BOE) tests are employed to characterize the chip strength. A probabilistic model is used to evaluate the failure probability. The contribution of different fabrication steps to the overall failure probability is investigated. A parametric analysis is performed to analyze the impact of material choice and the thickness of the substrate and the interposer. A single-step sintered package with a 200
$\mu\mathrm{m}$
thick Cu interposer and an 800
$\mu\mathrm{m}$
thick Cu substrate with hard Cu leads to a 12% failure probability compared to 52% for an identical stack with a soft Cu substrate. The top surface failure probability for a 150
$\mu\mathrm{m}$
thick CIC interposer is 0.016% compared to 8.6% for a 100
$\mu\mathrm{m}$
Cu interposer., for an identical
$800\mu \mathrm{m}$
thick Cu substrate. A sinterlamination process, where the die-attach and curing of the prepreg material simultaneously take place, results in a 0.03% failure probability.