Hardware Simulation of BRAM Digital FIR filter for Noise Removal of ECG Signal

The different ECG systems may have different computer programs, each using a certain algorithm(s) to do its interpretation. A physician is only as good as their training and their effort to continually educate and improve themselves. The motivation of this paper is to optimize the Delay and Power constraints in portable ECG devices. In this paper, the authors can get high computational density which helps make Flexible architecture of portable devices. The main aim of this paper is to design and implement a different circuit to denoise ECG signals using an FPGA Zedboard board. The higher sampling rate is the advantage of FPGA for designing a digital filter application over DSP chips and it is also cost-efficient than ASIC for moderate volume application. We can pre-process the ECG signal using the VIVADO tool. In this paper, the authors have used fixed-point representation with variable length.