Design and Simulation of 32 X 8 Kb Random Access Memory Composed of Reciprocal Magnetic Flux Quanta

By 2020, CMOS (complementary metal-oxide semiconductor) technology will be obsolete, and Post Moore law technology will be vying for low-power, high-speed operation. With both speed and energy economy, high-performance computing is in high demand. One of the technologies that will produce high speed and minimal static power dissipation is Reciprocal Quantum Logic (RQL). Instead, then using a DC power supply, RQL employs an AC power supply. To avoid power loss and achieve high speed, a series of reciprocal transmission lines are built between each gate. CMOS technology has been used in a variety of RAM (Random Access Memory) developments. VHDL (VHSIC Hardware Description Language) is used to design a 32 X 8 Kb RAM cell. VHDL is a hardware description language that is used to design EDAs (Electronic Design Automation). To adopt superconductor logic, random access memory cells are first synthesized and then simulated using HDL software, which provides IEEE standards 1076 2002. Power is measured using Xilinx Vivado design suite after implementation and those power is compared to find efficient design