Design of Low Power Adaptive Path Changing Glitch Free Radix-4, Radix-8 Multipliers

The emerging growth of digital systems depends on the errorless implementation of signal processing circuits. These circuits are implemented in VLSI platforms that provide reconfigurable clocking circuits. The clock signals are required to be stable and glitch free. In most of the digital circuit developments, multiplier plays a major role. The design implemented with less number of multipliers is highly demanded. These multiplier circuits are highly sensitive to glitches that occur due to fluctuations in power and floating elements. The proposed approach uses the RADIX-4 and RADIX-8 models with a glitch optimization circuit to construct a low power adjustable path selective Booth Multiplier architecture. The system utilized low power techniques like clock gating and sequenced latching process. The design is simulated using Modelsim tool and validated with test and evaluation of multiplier circuit with equivalent test bench. In comparison to the circuit with glitches, this model achieves low power elements after removal of glitch.