Chip-Package interaction stress analysis and optimization for a 14nm extreme low-k chip of FCCSP package

In this paper, Chip-Package interaction(CPI) stress during chip attach reflow process were analyzed by FEM. Furthermore, there is a much distinct scales difference between 15mm×15mm FCCSP package and extreme low-k (ELK) chip, submodeling techniques had been used in this study to bridge the scale gap. Firstly, in order to get more accurate CPI stress in the submodel, it’s necessary to locate the weakest bump. A FEM thermal-mechanical stress analysis with global package model was conducted. In this global model, the PSV and PI layer weren’t established. The result showed the maximum stress of package appeared on the left lower side of the chip. Secondly, according to the simulation results of the global model, a 1/4 model of the package was established to reduce simulation time. Then, according to the 1/4 model simulation results, we establish submodel, which the PSV opening size is 40um, the PI opening size is 30um, and the bump size is 45um×70um, the chip thickness is 150um, and then the submodel simulation was carried out. So far, the detailed CPI stress was obtained. Finally, 4 structural parameters were chosen to conduct DOE analysis evaluating the effects on CPI stress, including of chip thickness, PSV opening size, PI opening size and bump size. The results showed that the stress of the ELK layer was directly concerned with the structural characters. By optimization on structure properties of the FCCSP package, the stress of the ELK layer can be reduced to the relatively safe level.