Low Power State Assignment of Sequential Circuits based on Binary Particle Swarm Optimization and Flip-Flop Selection

State assignment is one of the essential aspects of logic synthesis and optimization of sequential circuits’ area and power. To find the exact state encoding which gives minimum power for a particular circuit is an NP-hard problem and thus time-consuming. This paper proposes a modified Binary Particle Swarm optimization (BPSO) state assignment problem with sequential element selection to find low power for multi-level realization circuits. The state assignment algorithm minimizes the Boolean distance between the states’ codes with high state transition probability and hence minimizes the weighted Hamming distance as the generation of the algorithm evolves. Apart from identifying good codes for the states, the approach also makes a judicious selection between D- and T-type flip-flops for individual state bits. Experimental results for a number of LGSynth89 benchmark FSMs have shown the superiority of the approach over other methods reported in the literature, both in terms of solution quality and runtime requirements. The experimental result for the proposed BPSO state assignment algorithm produces 1.76%, 26.78%, and 5.74% less power than all existing techniques such as PTS, MPES and PPSS, in terms of solution quality and runtime requirement.