A New Circuit for Efficient and Robust Two-Phase Delay-Insensitive Global Communications

The communication between many resources for System-on-Chip (SoC) design in modern Integrated Circuits (ICs) is a challenge due to significant wire delays in Deep Sub-Micron MOS (DSM-MOS) technology, and an increase in latency and power consumption is a problem in synchronous systems. As an alternative, asynchronous circuits, that uses handshake protocols can be used to decrease this problem. Asynchronous handshake protocols are two-phase or four-phase, and both of them provide good advantages over the other. In this paper, we propose a new circuit for efficient and robust conversion between the Level-Encoded Dual-Rail (LEDR) code, which operates in the two-phase protocol, and the traditional dual-rail code. The proposed circuit was synthesized in Field Programmable Gate Arrays (FPGA) for experimental validation, which achieved an average reduction in latency of 6.31% and an average increase of 9.95% in throughput compared with other proposal from the literature.