Performance Evaluation of Fault-Tolerant Routing Methods Using Parallel Programs

Toward the realization of high-end consumer electronics products, fault-tolerant rouging plays a key role in communication among nodes in Network-on-Chip-based manycore embedded systems. A variety of fault-tolerant routing methods have been studied with the evaluation on the communication performance such as communication latency and network throughput. However, such evaluation is not practical in that it cannot reveal the difference of performance between the target routing methods in executing parallel applications. For this problem, we propose an evaluation method of fault-tolerant routing methods using real parallel programs. Our method allows designers of routing methods to easily incorporate the information obtained from a parallel program into the conventional routing simulations. Evaluation with the proposed method shows that the fault-tolerant routing method called Passage-XY reduces execution time of Integer Sort (IS), which is one of the parallel programs in NAS parallel Benchmarks, by about 56%, compared with the region-based method called Position Route.