An Area Efficient Low-Power mmWave PRBS Generator in FDSOI

This paper presents a miniature, low-power pseudo-random binary sequence (PRBS) generator based on true single-phase-clock (TSPC) flip-flops that form a linear-feedback shift register (LFSR). Operating at a supply voltage of 0.88 V it generates a 2
¹¹
-1 m-sequence with a maximum data rate of 33 Gb/
s
. The circuit is fabricated in a 22-nm fully depleted silicon on insulator (FDSOI) CMOS technology and occupies a core area of only 42 µm
²
. With a core power consumption of only 1.3 mW at the maximum data rate, it is well suited for its application as a baseband signal generator in a phase-modulated continuous-wave (PMCW) radar transmitter. The PRBS generator exhibits a figure of merit (FoM) of only 8
^fJ
/bit. This is an improvement by the factor of five compared to the current state of the art to the best of authors' knowledge.