Design and Implementation of a 3.9-to-5.3 GHz 65 nm Cryo-CMOS LNA with an Average Noise Temperature of 10.2K

Realization of CMOS SoC readout solutions for future quantum computers will require demonstrating cryo-CMOS LNAs with cutting-edge noise and power. However, a lack of design models makes the systematic implementation of these devices challenging. Here, we propose a method for the first-pass design of cryo-CMOS LNAs by complementing room temperature PDK models with additional noise sources and report a cryo-CMOS LNA in 65nm bulk CMOS achieving > 38 dB gain and an average noise of 10.2K from 3.9-5.3 GHz while dissipating 23.1mW. The amplifier can be operated at < 10mW at a cost of 1K additional noise. Using a FOM representing the number of added noise photons, bandwidth, and power, the amplifier is shown to have a > 2x better FOM than other state-of-the-art cryo-CMOS LNAs. Additionally, we extract cryogenic noise models and find that the Fano factor for this technology does not appear to change with cryogenic cooling.