40nm Backside Optimization and Improvement

Wafer backside condition is a major and everlasting problem during IC manufacturing process in recent years, which may induce yield loss or increase energy consumption due to tool alarm. In this paper we design a simple way to maintain backside nitride film to protect wafer backside from high etch rate acid erosion during cleaning. The leveling and backside flatness are efficiently improved, which is extremely promising for wafer backside uniformity improvement and wafer yield enhancement.