Improvement of CMOS Device Performance by a Combination of Spike and Flash Annealing

As the size of semiconductor devices scales down, the fabrication of devices calls for highly activated source/drain with as little diffusion as possible. Continuing a trend that began with rapid thermal annealing (RTA), anneals continue to shrink in time and increase in temperature. This paper describes a fabrication process that uses a combination of spike RTA, laser spike annealing (LSA) and flash lamp annealing (FLA) and the device characteristics of product wafers showed positive results. The superior electrical characteristics of NMOS transistors whose gate length is less than 50nm, which are fabricated by using the FLA process, are demonstrated and leads to better threshold-voltage (Vt) roll-offs. Vt roll-off, Vt-Ion, Ion-Ioff correlation have been reviewed, with FLA combined, core N and PMOS device performance gains 2.5% and 5% respectively. The main benefits of flash annealing for junction formation are low sheet resistance junctions with a high level of activation together with no or limited diffusion.