Increasing the Post Halo Implantation Anneal Temperature for the Effective Improvement of Threshold Voltage Roll-off Induced by the Unique Non-uniform Boron Diffusion from the Embedded Source/Drain

The severe threshold voltage (Vt) roll-off is revealed for PMOSFETs with the embedded SiGe source/drain (eSiGe S/D) when the gate length decreases. The unique non-uniform boron diffusion into the channel region from eSiGe is found to be the main reason, which is intrinsically caused by the sigma-shaped trench. Lowering the growth temperature of eSiGe is widely adopted to solve the Vt roll-off issue but with a very complicated adjustment of eSiGe growth process. Without the change of eSiGe growth process, a post halo implantation anneal at a higher temperature before the S/D trench etching is proposed and demonstrated to be able to effectively improve the Vt roll-off too, providing a new way to suppress short channel effect.