Integration Strategy on Low-Cost Chip-First Fan-Out Panel Level Packaging

In the fan-out packaging (FOP), a higher lithography cost induced by the reconstituted die shift has yet been overcome, especially in the gradually increased carrier size in recent advance, e.g. panel-level-packaging (PLP). Our previous study demonstrates that with proper die shift compensation, the post-molding/grinding 3-sigma die shift value in X and Y for the whole panel with size of
$510\text{mm}\times 515$
mm are over 200um. The die shift data is collected and input into a software algorithm to synthesis a 99.8% photolithography yield within ±12um lithography overlay specification under an exposure field size that contains
$4\times 4$
die array (
$28.4\text{mm}\times 28.4\text{mm}$
). By confining the die shift induced by the mold flow and pre-shifting the die in consideration of the effective coefficient of thermal expansion of FOPLP, the post-molding/grinding die shift 3-sigma value in X and Y is then improved to 109um and 108um, respectively, rendering the exposure field size increasing to greater than 10 times (
$99.4\text{mm}\times 99.4\text{mm}$
) than that of
$4\times 4$
die array, meanwhile maintain the lithography yield at a comparable level.