A VLSI Digital Circuit Platform for Performing Deterministic Stochastic Computing in the Time Dimension Using Fraction Operations on Rational Numbers

Stochastic computing (SC) is a method of expressing values in streams of random bits and performing computation with bitwise operations on the streams. Recently, it was found that SC can be conducted on deterministic bitstreams where a numerical value is represented uniformly by sections of 1s and 0s. This leads to deterministic SC, where the computing result can be 100% accurate. However, at the current stage, its circuit implementation has not reached the level of practicality. Moreover, the expressible values for operands are theoretically limited. An all-digital frequency synthesizer, time-average-frequency direct period synthesis (TAF-DPS), is proposed here as a hardware platform for performing deterministic SC in the time dimension. The TAF-DPS is used as a rational-number-to-time converter (RNTC), transforming a rational number into an electrical waveform. Waveforms of unique frequencies and duty cycles are then generated according to the operand values. Instead of digital bitwise operations, each computation is carried out in the time regime on waveforms. Hence, it can be regarded as an “analog-like” logical operation. This RNTC-based time-domain operation opens up a subfield of SC: rational number stochastic computing (RN-SC). In RN-SC, fraction computation can be executed with logic gates, and the result is 100% accurate. The enabling factor is the improvement in resource utilization since the time dimension is exploited more efficiently. With this extra resource of time, expansion of the scope of SC is expected. In this article, the working principle is elucidated, and the circuit is discussed. Furthermore, a field-programmable gate array (FPGA) prototype is created to validate this platform for SC. The aim of this work is to create a practical tool for broadening the use of SC.