A Thermal Resistance Network Model of 3D-Stacked Stand-Alone MRAM

Unlike traditional memories such as SRAM and DRAM, STT-MRAM has many advantages, especially non-volatility, which has attracted the attention of many researchers in recent years. Nowadays, MRAM is one of the most competitive candidates for next-generation universial memory. Its power consumption is one of the important merits for its practical application to take the place of the incumbent memories in near future. For the stand-alone STT-MRAM with large capacity, the 3D-stacking technology is adopted to pile up multiple chips in the single package, in which a heat sink is applied on the top for the heat management. On this scenario, the spintronic devices in the memory need large switching current for fast switching speed, which requires more power consumption and heat fluxes in STT-MRAM chip. On the other hand, the 3D stacking architecture of STT-MRAM shows specific properties on the power budget and the thermal management. Therefore, it is necessary to establish a thermal model for the power-related 3D stacked MRAM in the early stage of the package architecture design. In this paper, a thermal resistance network model of the 3D-stacked MRAM is proposed for the thermal analysis of the 3D-stacked memory. The effects, including the number of stacked layers, the size of chips, the power density, and the heat dissipation capacity, are evaluated based on the established thermal model. The results show that this model facilitates the communication between the circuit designer responsible for power consumption and the package designer responsible for heat dissipation in the early stage of the MRAM design. The accuracy of the model is as the same as that of the finite element approach, showing its feasibility in evaluation of the thermal issues, with the benefits of the time-saving and cost-effective.