An Efficient area Neural Network Implementation using tan-sigmoid Look up Table Method Based on FPGA

Field-programmable gate arrays (FPGAs) are used in this paper to create neural networks in hardware (FPGAs). A neural network's different multipliers limit the size of the network that can be implemented using a single FPGA, making NN applications uncommercially viable and preventing non-linear activation functions from being run directly on an FPGA despite increases in FPGA density. As a result of this design, a larger neural network can be implemented on a single chip at a lower cost, while reducing the amount of resources required. In this work, the implementation of Data normalization and restructuring are used to create one type of neural network, whereas the lookup table method is used to implement another. On the Spartan-3A 3sd3400afg676-4 FPGA device, neural networks have been implemented. Using this architecture, resources will be optimized by 1% and 0% for slices and lookup tables (LUTs), as well as a specialized Flip Flop (FF).