Improved Cache Replacement Policy based on Recency Time Re-Reference Interval Prediction

The cache memory, having one of the fastest response times in the memory hierarchy (superseded only by processor registers), while also residing closest to the processor, has a major role in improving memory access times. While many different heuristics are involved in improving cache performance, the replacement policy plays a pivotal role. The work presents a novel replacement policy ‘Recency Time Based Re-Reference Interval Prediction’ (RT-RRIP), based on the concept of a recency time prefilter augmenting the performance of the re-reference interval prediction (RRIP) model, resulting in decrease in the number of cache misses and miss latency. An extensive analysis has been carried out using standardized SPEC CPU2006 benchmarks to compare the new policy with existing alternatives. Results reveal that the proposed cache replacement policy RT-RRIP has up to 12% performance improvement over RRIP and 4% performance improvement over LRU on average.