Dynamic Reconfiguration Processor for FIR Filter with High Speed, Low Power Consumption and High Flexibility

In order to meet the requirements of flexibility and scalability, a dynamic reconfigurable processor is designed to implement FIR algorithm. Firstly, this paper analyzes many different FIR structures; Secondly, a dynamic reconfigurable processor architecture and its workflow are designed, which includes an array of dynamic reconfigurable processing elements; Thirdly, this paper designs the input and output data flow, logic function and storage structure of each processing element; Finally, the simulation results show that the architecture can achieve low processing delay and high flexibility.