A Study on ESD-CDM Cross-Power Domain Failures

A study about Electrostatic Discharge-Charge Device Model (ESD-CDM) phenomena met in cross-power domain architectures is presented in this paper. The emphasis will be on the limitations of a protection method based on Grounded Gate nMOS (ggnMOS) device with different geometries in an advanced technology node. The considered CDM stress levels varied from 500V up to 2000V. The investigation is based on a test-chip implementation with all the designed architectures. For the recommended 500V CDM stress, a good protection is offered by a ggnMOS structure with channel length increased with at least 50% of the minimum value, in combination with any width in range of 120nm-1$\mu$m.