I. Introduction
With the rapid growth of market demand for portable mobile data access devices, the market's requirements for functional integration and packaging complexity are also increasing. At the same time, higher integration, better electrical performance, lower latency, and shorter vertical interconnect requirements are forcing packaging technology to shift from 2 packaging to more advanced 2.5 and 3 packaging designs. To meet these demands, various types of stacked integration technologies are used to integrate multiple chips with different functions into smaller and smaller sizes. Even so, the key factors that affect the packaging challenges are still similar, such as cost-effective manufacturing process, fine pitch interconnect within the micro-behavior, and so on. Specifically, they are in the chip / wafer level miniaturization and integration issues that must be overcome [1]-[2].