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A Novel Equivalent Model for Underfill Molding Process On 2.2D Structure for High Performance Applications | IEEE Conference Publication | IEEE Xplore

A Novel Equivalent Model for Underfill Molding Process On 2.2D Structure for High Performance Applications


Abstract:

A novel methodology of 3D CAE modeling of capillary underfill of multi-chip packages with a large number of micro bumps is employed in this study. The capillary underfill...Show More

Abstract:

A novel methodology of 3D CAE modeling of capillary underfill of multi-chip packages with a large number of micro bumps is employed in this study. The capillary underfill flow is mainly driven by the surface-tension force based on the contact angle between bumps and substrate. On the other hand, the propagation of the melt front is mainly dominated by the dispensing design of underfill and the distribution of micro bumps. For the simulation of dispensing behavior, 3D modeling is unavoidable. However, the computing cost will become unaffordable due to the number of bumps. To ease the computing cost, an equivalent technique -The Equivalent Bump Group (EBG) model is proposed to the simulation. A simple package is studied to validate the proposed methodology. The case shows that the modeling solution of melt front by EBG model has a good agreement to the detailed model by according dispensing passes. Therefore, it is convinced that the proposed methodology provides a promising simulation solution for the microchip encapsulation for multi-chip packages with large number of micro bumps. A study for a multi-array package of different dispensing designs by EBG model is also conducted. The result shows that filling time can be predicted to get the best dispensing design with minimum filling time.
Date of Conference: 31 May 2022 - 03 June 2022
Date Added to IEEE Xplore: 12 July 2022
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ISSN Information:

Conference Location: San Diego, CA, USA

I. Introduction

With the rapid growth of market demand for portable mobile data access devices, the market's requirements for functional integration and packaging complexity are also increasing. At the same time, higher integration, better electrical performance, lower latency, and shorter vertical interconnect requirements are forcing packaging technology to shift from 2 packaging to more advanced 2.5 and 3 packaging designs. To meet these demands, various types of stacked integration technologies are used to integrate multiple chips with different functions into smaller and smaller sizes. Even so, the key factors that affect the packaging challenges are still similar, such as cost-effective manufacturing process, fine pitch interconnect within the micro-behavior, and so on. Specifically, they are in the chip / wafer level miniaturization and integration issues that must be overcome [1]-[2].

References

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