A Novel Multiplier Hardware Organization for Finite Fields Defined by All-One Polynomials

In this brief, a novel, energy-efficient hardware organization for a finite-field multiplier based on irreducible all-one polynomials (AOPs) is proposed. The proposed AOP multiplier organization deploys three distinct submodules, which constitute a left-shifting network (reduction), an AND network (multiplication), and a three-input XOR tree (accumulation). Previously reported state-of-the-art implementation distributes these operations to systolic arrays, which are elegant in layout but do not yield the most efficient solution. The advantages of the proposed organization compared with those reported in the literature include reduced cost and power dissipation for a given clock frequency constraint (or increased clock frequency for a given power constraint) and the absence of bypassing problems due to fewer pipeline stages. Both the previously reported and the proposed organizations have been implemented in Verilog for three different binary-field sizes using the TSMC 90 nm standard cell library and have been synthesized for three distinct frequency targets using Cadence Genus Synthesis tool. The proposed organization achieves 18%, 31%, and 19% reduction in average leakage, dynamic capacitance, and area, respectively, compared with state-of-the-art schemes and thus can be considered for energy-efficient, compact portable systems, including wireless sensors.