Experimental Investigation of Dual-Gate LDMOS for Low On-Resistance

In this work, the dual-gate LDMOS has been firstly fabricated and reported based on the 0.18μm BCD process. The hard nut of the experiment is the consistence of the threshold voltage (V
th
) between the planar gate and trench gate due to the same p-body. To overcome it, the V
th
compensation technology has been proposed without additional mask by adding an arsenic implantation after the trench etch process. After that, the V
th
of trench gate is decreased effectively for the proposed LDMOS. Based on it, the current capacity of the proposed LDMOS has been investigated that the current can be enhanced from 8% (linear region) to 22% (saturation region). In addition, considering the robustness of this kind of trench gate device, the high temperature gate bias (HTGB) reliability and the gate charge (Q
g
) has been studied for the proposed LDMOS. Meanwhile, its hot-carrier reliability also has been assessed comprehensively.