A Pathway to Improve the Reliability of p-GaN Gate HEMTs through Buffer Hole Accumulation

In this report, we investigate the trap-related mechanisms of the dynamic on-resistance (R
ON,dyn
) increase and short circuit capability of p-GaN Gate HEMTs and suggest a pathway to improve the reliability characteristics. The trapping phenomena that occur in the buffer during the device operation are analyzed by measuring the spatio-temporal potential in the drift region between the gate and drain. The wafer level transient voltage measurements confirm that both dynamic on-resistance degradation and short circuit deterioration can be improved by adjusting the hole traps in the buffer structure. Our new generation device with an optimized buffer structure shows less than 10 % of R
ON,dyn
increase even at 150 ℃ and 1000 s of offstress condition as well as the short circuit ruggedness.