A Pipelined Algorithm and Area-Efficient Architecture for Serial Real-Valued FFT

In this brief, we present a novel pipelined architecture for real-valued fast Fourier transform (RFFT), which is dedicated to processing serial input data. An optimized algorithm is proposed for stage division in RFFT to achieve an area-efficient RFFT computing structure with full hardware utilization. A single path butterfly and a real rotator are merged into one processing element (PE) in each stage, except the last stage, to reduce hardware resource utilization. In addition, a novel shift-adder is designed for
$N$
-point RFFT with
$W$
-bit signals, and a new data management method based on the PEs is proposed, which saves resources with a more regular flow graph.