A Low-Cost Novel Structure for Paralleled SiC JFET/Si MOSFET Cascodes to Balance Turn-on Current and Junction Temperature

SiC JFET/Si
mosfet
Cascodes (SSCs) are promising because of their small
on
-resistance and fast switching speed. Parallel operation of multiple SSCs is popular for high-current applications. However, the practical layout can hardly be absolutely symmetric. The mismatches from layout will cause turn-
on
current imbalance among paralleled SSCs. The maximum current stress will be aggravated for some SSCs. Besides, unbalanced current can lead to uneven losses. Then, the junction temperature difference (Δ
T
_j
) between paralleled SSCs occurs. The maximum junction temperature (
T
_jmax
) among paralleled SSCs increases accordingly. To address the issue, a low-cost and novel structure is proposed to promote turn-
on
current sharing for paralleled SSCs. With aid of the structure, the immunity of turn-
on
current sharing performance to an asymmetric layout can be greatly improved. The mismatched turn-
on
current and losses can be well mitigated. Δ
T
_j
and
T
_jmax
are suppressed at the same time. The proposed structure is suitable for both the discrete SSCs and bare-die SSCs. In this structure, only some bridging branches are introduced so it takes almost no extra cost. Two prototypes are fabricated with the discrete SSCs and bare-die SSCs, respectively. Double-pulse test and continuous operation are conducted to validate the advantages of the proposed structure.