Hybrid Successive Subtraction Method of Analog to Digital Converter

Two techniques of successive subtraction type of analog to digital converter (SSADC) topology, one that uses N-different reference voltages for an N-bit SSADC (NR SSADC) and the other with just one reference voltage (OR SSADC), are analyzed to identify the shortcomings in the methods. A novel hybrid successive subtraction method of analog to digital converter (HSSADC) that exploits the advantages of both the schemes and overcomes the shortcomings of both methods is presented here. The proposed HSSADC technique is analyzed and studied through simulation. The simulation results validate that the proffered HSSADC technique provides better performance than either the NR SSADC or OR SSADC, especially at higher resolution. The proffered HSSADC is compared with existing techniques.