An FPGA Online Fault Location based on Bitstream Copy and Programmable LFSR

In order to improve the reliability of SRAM-based field programmable gate array (FPGA) in various harsh environments, an FPGA online fault location method with high accuracy needs studying to support subsequent fault tolerance technologies. To achieve FPGA online fault location, it is necessary to overcome a series of limitations such as a lack of hardware resources and a lack of user design knowledge. Therefore, this paper proposes a black box fault location method based on meshed bitstream copy. Generally, the linear feedback shift register (LFSR) is used in application-dependent fault locations to achieve exhaustive testing. As the scale of user design increases, the test complexity increases exponentially, and LFSR can only support small-scale application circuits. The method proposed in this paper divides the FPGA resources into small meshes, and copies the under-test mesh to adjacent areas by the bitstream copy. It applies the same test pattern to both meshes and compares the results to identify if there is a fault. This paper focuses on how to achieve the connection between the under-test mesh and the test structure, proposes a programmable universal linear feedback shift register, and presets a number of test routines connected to the under-test area in advance. By comparing the preset bitstream with the original under-test bitstream, we can find an available routine in preset bitstreams. The connection between the under-test mesh and the programmable linear feedback shift register is realized by modifying the corresponding bits of the under-test mesh. A ring oscillator with high resource utility is adopted for demonstration. Fault injection and fault location experiments are carried out on current mainstream FPGAs.