A Flexible Hardware Accelerator for Morphological Filters on FPGA

Nowadays, the demand for embedded image processing, especially for computer vision applications is growing. Digital image processing is seeing intensive use in real time applications for several areas, such as the industrial environment, military equipment, automobile, entertainment, and medical instruments. Mathematical Morphological theory, offers a wide variety of tools, applied efficiently in most image processing steps at different scales, like image enhancement, segmentation, and classification. Therefore, such features yield a high potential of reconfiguration in image processing blocks. Morphological opening and closing operators are used as primary blocks in diverse image processing applications such as image cleaning and contrast enhancement. Moreover, using appropriate shapes and scales of structuring elements(SE), provides more flexibility and can significantly improve the enhancement performance. Nevertheless, such operators can be computationally intensive due to the increased complexity and the significant memory requirement. Also, the use of high image resolution and reconfigurable size and shape of structuring elements may deepen this limitation significantly. In this paper, we consider hardware acceleration on FPGA as a promising solution to raise the above mentioned-challenges. Both intra-level and inter-level parallelism techniques based on the reuse of optimized dilation and erosion blocs are exploited to accelerate computation and save memory consumption. Unlike most existing works, this paper proposes a highly flexible architecture for opening and closing-based morphological filters. The architecture supports re-configurable shapes and sizes of structuring elements while keeping a high ability to meet real-time processing requirements and low power consumption. An improvement in terms of frame rates up to 8% with more than 2000 Fps for moderate size of structuring elements and high image resolution is achieved.