Two-Mask Wafer-Level Vacuum Packaging With Bulk-Si 3D Interconnects for MEMS Devices and Its Package Performances

We present the novel 3D wafer-level vacuum packaging technology for MEMS, which only needs two masks and is realized by Au-Si eutectic bonding with a low-resistivity Si Cap wafer. Wherein, Au-Si bonding pads and rings are formed to accomplish vertical interconnects and a vacuum package respectively. Applied to resonators with two typical substrate wafers of Si and Glass, this 3D package structure has further gone through the systemic characterizations. Specifically, the high-reliable mechanic strengths of device packages are revealed from Au-Si bonding strengths measured as about 20 MPa in tensile tests. Based on analyzing parasitic capacitance networks in device packages, the feed-through effect in resonance tests can be effectively relieved by grounding on each Si layer in device package structures (i.e. the parasitic capacitance reduced from the level of pF to fF). By resonance tests, it is found that increasing the degassing duration (30 min
$\to 60$
min
$\to 100$
min) is beneficial for improving package vacuum degrees as well as consistencies (69% within 4–30 kPa
$\to 88$
% within 0.6-1.2 kPa
$\to 85$
% within 0.6-0.8 kPa), and hermetic package yields (73%
$\to 86$
%
$\to 100$
%). Besides, device packages are verified to have good long-term stability by monitoring quality factor variations in 6 months. Overall, this proposed 3D packaging technology has extensive application prospects in various MEMS devices due to its inherently-simple process, low capacitive feed-through effect, and fine package performances. Also, test results provide instructions on the realization of low-parasitic-capacitance signal interfaces and the optimization of wafer-level vacuum package processes.