Design Of High-Speed Vedic Multiplier Using Urdhva Tiryakbhyam Sutra

The suggested effort aims to improve the binary Vedic multiplier utilizing Vedic ideas and old Vedic mathematics. It alters the current Vedic multiplier in terms of time delay, area, and power usage to obtain a better outcome. Nowadays in integrated circuits, additions are almost a standard necessary to get good results. The adders must meet two criteria: first, they must be quick, and second, they must be energy efficient in terms of power usage and chip area. The paper presents a valuable alternative method for choosing an adder combination that balances delay, power, and area. The adders employed in this design are the carry look-ahead adder, carry select adder, and carry skip adder. The solution is simplified to a considerable extent in ancient Vedic mathematics, making the entire procedure more efficient. In Verilog, the desired Vedic multiplier is enforced and in Xilinx tool 14.7, the amalgamation and simulation are done.