Static and Dynamic power optimization using Leakage Feedback approach for nanoscale CMOS VLSI circuits

Packaging density and operating speed are common considerable issues in today's deep submicron regime. If packaging density has to be increased then transistor size and channel length should be decreased. Due to short channel effects in submicron regime. Decreasing channel length decreases the threshold voltage. Decreasing threshold voltage also increases the power dissipation due the subthreshold leakage current. By carefully designing the sleep transistors with an added leakage current feedback transistor, effectively decreases the static and dynamic power dissipation along with delay introduced due to sleep transistors. The proposed technique is applied to design a logic circuit to efficiently reduce static, dynamic power dissipation with increase performance.